The present invention relates generally to floating gate stacks commonly found in floating gate memory cells, and in particularly to floating gate stacks having a metal control gate protected from oxidation during oxidation of the floating gate, methods of their fabrication and apparatus produced therefrom.
A flash memory device is a non-volatile memory, derived from erasable programmable read-only memory (EPROM) and electrically-erasable programmable read-only memory (EEPROM). Flash memory is being increasingly used to store execution codes and data in portable electronic products, such as computer systems.
A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge, and is separated, by a layer of thin oxide, from source and drain regions contained in a substrate. Each of the memory cells can be electrically programmed (charged) by injecting electrons from the drain region through the oxide layer onto the floating gate. The charge can be removed from the floating gate by tunneling the electrons to the source through the oxide layer during an erase operation. Thus the data in a memory cell is determined by the presence or absence of a charge on the floating gate.
Flash memories have a typical operating voltage in the range of about 1.8 to 5 volts. A high voltage, however, is usually required for programming and erase operations in a flash memory. This high voltage (Vpp) is in the range of the 10 to 13 volts, but can be higher. During a programming operation, electrons are injected onto the floating gate by applying the high voltage (Vpp) to the control gate and about one-half Vpp to the drain region while the source region is grounded. Electron tunneling from the floating gate during an erase operation is accomplished by applying Vpp to the source region, connecting the control gate to ground potential and leaving the drain region electrically unconnected or floating. Alternately, a large negative voltage could be applied to the gate and a higher voltage applied to the source to perform a negative gate erase operation.
The construction and operation of a basic stacked floating gate memory cell is described with reference to FIGS. 1A, 1B and 1C. FIG. 1A is a cross-sectional view of a typical floating gate memory cell used in flash memories. Memory cell 100 comprises a source region 102 and a drain region 104. Source 102 and drain 104 are constructed from N+ type regions formed in a P-type semiconductor substrate 106. Source 102 and drain 104 are separated by a channel region 108. Memory cell 100 further includes a floating gate 110 formed by a first polysilicon layer, and a control gate 114 formed by a second polysilicon layer. Floating gate 110 is isolated from control gate 114 by an interpoly dielectric layer 112 and from channel region 108 by a thin gate oxide, or tunnel layer 116. The source region 102 generally has a deeper junction than the drain region 104 for improving erase operations.
FIG. 1B is the memory cell 100 of FIG. 1A during a programming operation. To program the memory cell 100 to store a charge, a positive programming voltage of about 12 volts is applied to control gate 114. This positive programming voltage attracts electrons 120 from P-type substrate 106 and causes them to accumulate toward the surface of channel region 108. The drain 104 voltage is increased to about 6 volts, and source 102 is connected to ground. As the drain-to-source voltage increases, electrons 120 begin to flow from source 102 to drain 104 via channel region 108. Electrons 120 acquire substantially large kinetic energy and are referred to as hot electrons.
The voltage difference between control gate 114 and drain 104 creates an electric field through tunnel layer 116, this electric field attracts the hot electrons and accelerates them towards floating gate 110. Floating gate 110 starts to trap and accumulate the hot electrons, beginning the charging process. As the charge on the floating gate increases, the electric field through tunnel layer 116 decreases and eventually loses it capability of attracting any more of the hot electrons. At this point, floating gate 110 is fully charged. The charged floating gate 110 raises the memory cell 100""s threshold voltage (Vt) above logic 1 (High) voltage. Thus, when control gate 114 is brought to a logic 1 (High) during a read operation, the memory cell 100 will barely turn on. As known to those skilled in the art, sense amplifiers are typically used in a memory to detect and amplify the state of the memory cell.
FIG. 1C is the memory cell 100 of FIG. 1B during an erase operation. The memory cell 100 is erased by discharging the floating gate. To erase the memory cell 100, a positive voltage of about 12 volts is applied to source 102 while control gate 114 is connected to ground and drain 104 is left unconnected, electrically floating. Alternately, a negative voltage, such as 10 volts, can be applied to the control gate while the source is coupled to 5 volts. With a higher relative voltage at source 102, negatively-charged hot electrons 120 are attracted and tunneled to source 102 through the tunnel layer 116. The tunneling is stopped when the floating gate is discharged. The lack of negative charge on floating gate 110 returns the memory cell 100""s threshold voltage below logic 1 voltage. Thus, when a voltage on control gate 114 is brought to a logic 1 during a read operation, the memory cell 100 will turn on. While the construction and operation of memory cell 100 are typical of the general concept of floating gate memory cells, those skilled in the art will recognize that the foregoing description is not intended to cover all variations of floating gate memory cells known in the art.
As device sizes continually decrease, operating voltages must decrease. Reduced operating voltages generally require reduced gate resistance for acceptable operating characteristics. In addition, the realities of self-aligned contact (SAC) processing call for reduced gate height as devices are packed more tightly in the available die real estate.
Tungsten has been identified as one approach for reducing gate height and gate resistance for field-effect transistor (FET) gates in general. Tungsten, however, is incompatible with oxidation processes, causing peeling, stress and related problems with the tungsten layer. One solution to using tungsten in FET gates has been to selectively oxidize the gate sidewalls in an H2O/H2 ambient. This ambient will oxidize the polysilicon sidewalls, but not the tungsten portion, thus eliminating the oxidation problems associated with tungsten. However, exposure of floating gate memory cells to water and hydrogen is known to cause certain reliability, erase uniformity and yield problems, so it is desirable to avoid this process in the case of floating gate memory cells. Yet the sidewalls of the floating gate must generally be oxidized in order to limit charge loss on the floating gate to acceptable levels, often on the order of one to two electrons per day.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved flash memory gate stacks and methods of their fabrication.
One embodiment of the invention includes a floating gate stack. The floating gate stack includes a first polysilicon layer, a dielectric layer over the first polysilicon layer, a second polysilicon layer over the dielectric layer, and a barrier layer over the second polysilicon layer. The floating gate stack further includes a metal layer over the barrier layer and a cap layer over the metal layer. An oxidation barrier is adjacent sidewalls of at least the metal layer and a sidewall oxide layer is adjacent sidewalls of at least the first polysilicon layer.
Another embodiment of the invention includes a floating gate stack. The floating gate stack includes a first polysilicon layer, a second polysilicon layer and a dielectric layer interposed between the first polysilicon layer and the second polysilicon layer. The floating gate stack further includes a metal layer, a barrier layer interposed between the metal layer and the second polysilicon layer, and a cap layer over the metal layer. An oxidation barrier is adjacent sidewalls of at least the metal layer, and a sidewall oxide layer is adjacent sidewalls of at least the first polysilicon layer.
A further embodiment of the invention includes a method of forming a floating gate stack. The method includes forming a polysilicon floating gate, forming a metal control gate and forming a dielectric layer interposed between the polysilicon floating gate and the metal control gate. The method further includes forming an oxidation barrier on sidewalls of the metal control gate, and oxidizing sidewalls of the polysilicon floating gate subsequent to forming the oxidation barrier on the sidewalls of the metal control gate.
A still further embodiment of the invention includes a method of forming a floating gate stack. The method includes forming a first polysilicon layer over a tunnel layer, forming a dielectric layer over the first polysilicon layer, patterning the first polysilicon layer and the dielectric layer using the tunnel layer as a stopping layer and forming a second polysilicon layer over the dielectric layer. The method further includes forming a barrier layer over the second polysilicon layer, forming a metal layer over the barrier layer, forming a cap layer over the metal layer, and patterning the second polysilicon layer, the barrier layer, the metal layer and the cap layer using the dielectric layer as a stopping layer to form a control gate. The method still further includes forming an oxidation barrier over the control gate, anisotropically removing a portion of the oxidation barrier to leave a remaining portion adjacent at least the metal layer, patterning a remaining portion of the first polysilicon layer and the dielectric layer using the cap layer and the remaining portion of the oxidation barrier as a mask, and oxidizing sidewalls of the first polysilicon layer subsequent to forming the oxidation barrier, thereby forming a sidewall oxide layer adjacent at least the first polysilicon layer.
Further embodiments include floating gate stacks and methods of forming floating gate stacks of various scope, as well as apparatus produced therefrom.